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XRT8020
650 MHZ CLOCK & CRYSTAL MULTIPLIER WITH LVDS OUTPUTS
NOVEMBER 2003 REV. 1.0.2
DESCRIPTION
The XRT8020 is a monolithic analog phase locked loop that provides a high frequency LVDS clock output, using a low frequency crystal or reference clock. It is designed for SONET/SDH and other low jitter applications.The high performance of the IC provides a very low jitter LVDS clock output up to 650 MHz, while operating at 3.3 volts. The XRT8020 has a selectable 8x, 16x or 32x internal multiplier for an external crystal or signal source. The Output Enable pin provides a true disconnect for the LVDS output. The very compact (4 x 4 mm) low inductance package is ideal for high frequency operation. APPLICATIONS * Gigabit Ethernet * SONET/SDH * SPI - 4 Phase 2 * 8x, 16x or 32x Clock Multiplier for Computer and Telecommunication Systems FIGURE 1. BLOCK DIAGRAM OF THE XRT8020
15-40 MHz Crystal XTAL1
12 - 20 pF
FEATURES * 575 MHz to 675 MHz operating range * Low Output Jitter: 9ps rms typical at 622 MHz * On Chip Crystal Oscillator Circuit * Optimized for 15 to 40 MHz crystals * Uses parallel fundamental mode crystal * Selectable 8x, 16x or 32x multiplier * Selectable / 1 or / 2 LVDS output * LVDS output meets TIA/EIA 644A Specification (2001) * 3.3V 10% Low power CMOS: 80 mW typical * -40C to +85C operating temperature * Extremely small 16-lead QFN package
+3.3V AVDD AVDD REXT 10k OVDD
XTAL2
12 - 20 pF
XRT8020
Voltage Reference & Bias Generator
Oscillator Circuit & Input Buffer
VCO Calibration Logic Phase Detector Charge Pump Loop Filter VCO Selectable / 1 or / 2 Divider OUTP LVDS Output OUTN
Feedback Divider / 8, 16 or 32
AGND (Crystal)
AGND
AGND
FS1
FS0
PD
OE
OGND
Exar Corporation 48720 Kato Road, Fremont CA, 94538 * (510) 668-7000 * FAX (510) 668-7017 * www.exar.com
XRT8020 650 MHZ CLOCK & CRYSTAL MULTIPLIER WITH LVDS OUTPUTS
REV. 1.0.2
FIGURE 2. XRT8020 PIN LOCATION - (TOP VIEW)
16
15
14
13
1 2
12 11
XRT8020
3 4 10 9
5
6
7
ORDERING INFORMATION
PART NUMBER XRT8020IL PACKAGE 16 - Pin QFN OPERATING TEMPERATURE RANGE -40C to +85C
2
8
XRT8020
650 MHZ CLOCK & CRYSTAL MULTIPLIER WITH LVDS OUTPUTS
REV. 1.0.2
DESCRIPTION .................................................................................................................... 1
APPLICATIONS ......................................................................................................................................... FEATURES ................................................................................................................................................ Figure 1. Block Diagram of the XRT8020 ........................................................................................ ORDERING INFORMATION ............................................................................................................... Figure 2. XRT8020 Pin Location - (Top View) ................................................................................. ABSOLUTE MAXIMUM RATINGS ....................................................................................................................... ELECTRICAL CHARACTERISTICS ..................................................................................................................... Figure 3. LVDS Output Waveforms and Test Circuits .................................................................... 1.0 Calibration ................................................................................................................................................. TABLE 1: FREQUENCY SELECTION TABLE .............................................................................................. TABLE 2: POWER-DOWN AND OUTPUT TRI-STATE SELECTION TABLE ....................................................... 2.0 Crystal selection ....................................................................................................................................... 3.0 data and plots ........................................................................................................................................... Figure 4. Input Referenced Jitter Connection Diagram ................................................................. Figure 5. Simplified Block Diagram of the XRT8020 and PECL Receiver .................................... Figure 6. LVDS Differential Output .................................................................................................. Figure 7. PECL Differential Output .................................................................................................. Figure 8. PECL Single-Ended Outputs (Positive and Negative Output Referenced to Ground) 1 1 1 2 2 3 3 5 5 5 5 6 6 6 7 7 8 9
ORDERING INFORMATION ............................................................................................. 10
REVISIONS ................................................................................................................................................. 11
I
XRT8020
REV. 1.0.2
650 MHZ CLOCK & CRYSTAL MULTIPLIER WITH LVDS OUTPUTS
PIN DESCRIPTION
PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 NAME AVDD AGND XTAL1 XTAL2 AGND REXT OE PD FS1 FS0 AGND OGND OUTN OUTP OVDD AVDD O O I I I I I I O TYPE DESCRIPTION 3.3V 10% Analog Supply for Crystal Oscillator Analog Ground for Crystal Oscillator Crystal pin 1 or external clock input Crystal pin 2 (output drive for crystal) Analog Ground External Bias Resistor (10K to ground) Output Enable, Active low (Internal 50K pull-down to ground) Power Down, Active High (Internal 50K pull-down to ground) Frequency select "1" (Internal 50K pull-down to ground) Frequency select "0" (Internal 50K pull-up to VDD) Analog Ground Output Ground for LVDS outputs LVDS negative output for 50 line LVDS positive output for 50 line 3.3V 10% Digital Supply for LVDS Output buffer 3.3V 10% Analog Supply
ABSOLUTE MAXIMUM RATINGS
Supply voltage VIN Storage Temperature Operating Temperature ESD REXT (1%) -0.5 to 6.0 V -0.5 to 6.0 V -65C to + 150C -40C to + 85C >2,000 volts 10k
ELECTRICAL CHARACTERISTICS
PARAMETER Supply Voltage Supply current Power Save Current Input Digital High Input Digital Low Crystal Frequency SYMBOL VDD IDD IDD VINH VINL 15 2.0 0.8 27 MIN 3.0 TYP 3.3 25 MAX 3.6 30 6 UNIT V mA mA V V MHz VDD = 3.3V VDD = 3.3V, PD = 1, OEB = 0 Pins 7, 8, 9, 10 Pins 7, 8, 9, 10 See Section 2.0 for Crystal Selection CONDITIONS
3
XRT8020 650 MHZ CLOCK & CRYSTAL MULTIPLIER WITH LVDS OUTPUTS
PARAMETER Crystal Frequency Clock Input Frequency Power on Calibration time SYMBOL MIN 27 72 TYP MAX 40 85 5 UNIT MHz MHz ms CONDITIONS See Section 2.0 for Crystal Selection AC Coupled (FS0=1, FS1=1) After VDD reaches 2.8V NOTE: Calibration time = 16,000 clock cycles 624 MHz nominal FOUT (See Table 1) 312 MHz nominal FOUT (See Table 1) CL = 5pF, RL = 100, (20% - 80%) CL = 5pF, RL = 100, (20% - 80%) LVDS output See Figure 3
REV. 1.0.2
Max Frequency Out Max Frequency Out Rise time Fall Time Duty cycle Differential Output Skew Output Loading Output Voltage Swing Common Mode Voltage Output Short Circuit Current Cycle-to-Cycle Jitter Cycle-to-Cycle Jitter Accumulated Jitter Accumulated Jitter Input Referenced Jitter Input Referenced Jitter
FOUT FOUT TR TF
575 285 350 350 45 10 100
675 340
MHz MHz ps ps
55
% ps
VOUT VCM
250 1.0 1.2 -5.7 3 3 12 12 9 9
450 1.4 -10
mV V mA ps ps ps ps ps ps
Magnitude of (OUTP-OUTN)
Current limit to ground, VDD or Vp to Vn rms, at 624 MHz rms, at 312 MHz rms, at 624 MHz rms, 312 MHz rms at 622 MHz, See Figure 4 rms at 312 MHz, See Figure 4
4
XRT8020
REV. 1.0.2
650 MHZ CLOCK & CRYSTAL MULTIPLIER WITH LVDS OUTPUTS
FIGURE 3. LVDS OUTPUT WAVEFORMS AND TEST CIRCUITS
LDVS Levels Test Circuit OUTP 50 VOUT 50 OUTN VCM
LDVS Switching Test Circuit OUTP CL = 5 pF VOUT CL = 5 pF OUTN RL = 100
LDVS Transition Time Waveform OUTP
50% VCM (Differential) tskew 50%
OUTN
80%
80%
VOUT
20%
0V
0V (Differential) 20%
TR
TF
TABLE 1: FREQUENCY SELECTION TABLE
FS0 PIN 10 1 0 1 0 FS1 PIN 9 1 1 0 0 CRYSTAL OR CLOCK FREQUENCY 78.0 MHz Clock 39.0 MHz 19.5 MHz 19.5 MHz INTERNAL CAPACITOR NA 12 pF 20 pF 20 pF MULTIPLY RATIO 8x 16x 32x 32x OUTPUT DIVIDE 1 1 1 2 OUTPUT FREQUENCY 624 MHz 624 MHz 624 MHz 312 MHz
NOTES: 1. Use Parallel Fundamental mode crystal 2. FS0 has an internal 50K pull-up resistor to VDD 3. FS1 has an internal 50K pull-down resistor to GND
TABLE 2: POWER-DOWN AND OUTPUT TRI-STATE SELECTION TABLE
PD PIN 8 1 0 OE PIN 7 X 1 STATUS Outputs tri-stated and chip Powered-down Output tri-stated
NOTES: 1. "X" = Don't care 2. PD and OE have an internal 50K pull-down resistor to ground.
1.0 CALIBRATION
5
XRT8020 650 MHZ CLOCK & CRYSTAL MULTIPLIER WITH LVDS OUTPUTS
REV. 1.0.2
The XRT8020 synthesizer jitter performance is optimized by calibration of its Voltage Controlled Oscillator (VCO) upon initial power application. This power ON calibration procedure is automatic and completely transparent to the user. It is initiated automatically upon first application of VDD. In order to bring the center frequency of the VCO close to the desired output frequency, the VCO bias current is adjusted via a current DAC at initial power application. The center frequency of VCO is checked against input reference frequency and calibrated internally to the desired output frequency value. These bias voltage trim bits are then held in latches for as long as the VDD is held above 2.7V (minimum specified operational value of VDD). The user should note following important facts about this calibration procedure for proper operation of the XRT8020: * For proper operation of the chip and to achieve lowest jitter, the user should follow layout guidelines as described in the User Guide. * An input crystal of appropriate frequency should be connected at XTAL1 and XTAL2 pins before power is applied to the chip. * All VDD pins should be tied to 3.3V 10% simultaneously. * The power supply should turn on without bouncing below 2.0V smoothly to its specified value in no more than 50msec. * The calibration takes place during VDD ramp up between 2.6V to 3V values. Once the VDD reaches and maintains 3.0V, the chip retains the calibrated VCO bias voltages in internal latches for proper operation. * To change a widely different value of crystal or input reference frequency, it is recommended to power down the chip by bringing VDD to 0V and restarting after the change in frequency has occurred. 2.0 CRYSTAL SELECTION It is recommended that a Fundamental Mode Crystal be used as the timing reference of the XRT8020. The following part has been qualified by EXAR: CITIZEN Quartz Crystals 20 MHz : HCM49-20.000MABJT 40 MHz : HCM49-40.000MABJT 3.0 DATA AND PLOTS All plots were recorded using the following parameters and test setup: * VDD = 3.3 V * 2" 100 Differential Transmission Lines (from LVDS outputs to receiver inputs) * Fundamental Mode Crystal of 20 MHz * Vref = 1.5 V (PECL Receiver) FIGURE 4. INPUT REFERENCED JITTER CONNECTION DIAGRAM
Outp XRT8020 Outn 20.0Mhz Crystal Tektronix P6330 Differential Probe Channel 1
MAX9111ESA Channel 2
Tektronix P6245 TDS 500/600
Tektronix TDS7404
6
XRT8020
REV. 1.0.2
650 MHZ CLOCK & CRYSTAL MULTIPLIER WITH LVDS OUTPUTS
FIGURE 5. SIMPLIFIED BLOCK DIAGRAM OF THE XRT8020 AND PECL RECEIVER
100ohm Transmission Lines
XRT8010/20 Clock Synthesizer
LVDS-To-PECL Receiver
FIGURE 6. LVDS DIFFERENTIAL OUTPUT
LVDS Differential Outputs
Freq 640.1 MHz
Ampl 824.0 mV
Ch1
200 mV
M 500 pS
7
XRT8020 650 MHZ CLOCK & CRYSTAL MULTIPLIER WITH LVDS OUTPUTS FIGURE 7. PECL DIFFERENTIAL OUTPUT
REV. 1.0.2
PECL Differential Outputs
Freq
640.0 MHz
Ampl
1.42 V
Ch1
500 mV
M 500 pS
8
XRT8020
REV. 1.0.2
650 MHZ CLOCK & CRYSTAL MULTIPLIER WITH LVDS OUTPUTS
FIGURE 8. PECL SINGLE-ENDED OUTPUTS (POSITIVE AND NEGATIVE OUTPUT REFERENCED TO GROUND)
PECL Single-Ended Outputs POS Output
Freq(1) 640.3 MHz
Freq(2) 639.9 MHz
Ampl(1) 520.0 mV
Ampl(2) 528.0 mV
NEG Output
Ch1 Ch2 200 mV 200mV M 500 pS
9
XRT8020
650 MHZ CLOCK & CRYSTAL MULTIPLIER WITH LVDS OUTPUTS
REV. 1.0.2
ORDERING INFORMATION
PART NUMBER PACKAGE 16-Lead QFN OPERATING TEMPERATURE RANGE -40C to +85C
XRT8020IL
PACKAGE DIMENSIONS
16 LEAD QUAD FLAT NO LEAD (4 mm x 4 mm, 0.65 pitch QFN)
Rev. 1.01
Note: the actual center pad is metallic and the size (D2) is device-dependent w/ a typical tolerance of 0.3mm
Note: The control dimension is in millimeter.
SYMBOL A A1 A2 D D1 D2 b e L INCHES MIN 0.031 0.000 0.000 0.154 0.144 0.088 0.009 MAX 0.039 0.002 0.039 0.161 0.152 0.100 0.015 MILLIMETERS MIN MAX 0.80 0.00 0.00 3.90 3.65 2.24 0.23 1.00 0.05 1.00 4.10 3.85 2.54 0.38
0.0256 BSC 0.014 0 0.030 12
0.65 BSC 0.35 0 0.75 12
10
XRT8020
650 MHZ CLOCK & CRYSTAL MULTIPLIER WITH LVDS OUTPUTS
REV. 1.0.2
REVISIONS P1.0.1 Accumulated output jitter in electrical specs changed from 25 ps @ 624MHz to 20 @ 622Mhz and TBD to 20 ps @312Mhz. Pin 9 has internal a pull-down resistor instead of pull-up. Table 1 FS0 and FS1 bit pattern changed. P1.0.2 Changed typical jitter to 6ps and changed package to QFN P1.0.3 Corrected package dimension dimension "e" to 0.65 mm BSC. Updated electrical tables. Added descriptive sections on Calibration, Crystal Selection and Data and Plots. 1.0.0 Final Release. Added intrinsic jitter measurements to the electrical characteristics. 1.0.1 Changed the page numbering. Changed the QLP to QFN in the Features on page 1. 1.0.2 Changed the Package Drawing and Dimensions.
NOTICE EXAR Corporation reserves the right to make changes to the products contained in this publication in order to improve design, performance or reliability. EXAR Corporation assumes no responsibility for the use of any circuits described herein, conveys no license under any patent or other right, and makes no representation that the circuits are free of patent infringement. Charts and schedules contained here in are only for illustration purposes and may vary depending upon a user's specific application. While the information in this publication has been carefully checked; no responsibility, however, is assumed for inaccuracies. EXAR Corporation does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless EXAR Corporation receives, in writing, assurances to its satisfaction that: (a) the risk of injury or damage has been minimized; (b) the user assumes all such risks; (c) potential liability of EXAR Corporation is adequately protected under the circumstances. Copyright 2003 EXAR Corporation Datasheet November 2003. Reproduction, in part or whole, without the prior written consent of EXAR Corporation is prohibited. 11

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